Passive reference-sharing SAR ADC |
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| Affiliation: | 1. Laboratorio de Termodinámica de Procesos, Departamento de Ingeniería Química y Ambiental, Universidad Técnica Federico Santa María, Avda. España 1680, Valparaíso, Chile;2. Centro de Investigación en Alimentación y Desarrollo, A.C., Carretera a La Victoria km. 0.6, Hermosillo, México;3. Departamento de Ingeniería Química y Bioprocesos, Pontificia Universidad Católica de Chile, Avda. Vicuña Mackenna 4860, Santiago, Chile;1. University of Castilla-La Mancha, Escuela Técnica Superior de Ingenieros Industriales, 13071 Ciudad Real, Spain;2. Pontificia Universidad Católica de Chile, Industrial and Systems Engineering Department, Santiago, Chile;1. Institute for Electronic Design Automation, Technische Universität München, Munich, Germany;2. Institute of Microelectronic Systems, Leibniz Universität Hannover, Hannover, Germany;1. Departamento de Ingeniería Industrial, Universidad de Chile, Chile;2. Departement d’Informatique, École normale supérieure, France;3. Facultad de Matemáticas & Escuela de Ingeniería, Pontificia Universidad Católica de Chile, Chile;1. Departamento de Química, Módulo 13, Universidad Autónoma de Madrid, Campus de Excelencia UAM-CSIC Cantoblanco, 28049 Madrid, Spain;2. Laboratorio de Química Teórica Computacional (QTC), Facultad de Química, Pontificia Universidad Católica de Chile, Santiago, Chile |
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| Abstract: | Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fully differential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along with its theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sized capacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and 39.3 fJ per conversion step without considering the clock generator power consumption. |
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| Keywords: | Analog-to-digital converter (ADC) Passive charge-sharing (PCS) Passive reference-sharing (PRS) Successive approximation register (SAR) |
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