应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。

High-speed programmable frequency divider for 26GHz ~ 41GHz frequency synthesizer

According to the system index of 2 GHz - 41 GHz silicon-based phase-locked loop frequency synthesizer,this paper designs and implements a high-speed programmable integer frequency divider based on TSMC 45 nm CMOS technology. In this paper,the high-speed divider is realized by the injection locking structure frequency division structure. The structure can realize the frequency division range of 25 GHz to 48 GHz with input power of 0 dBm,and the lowest power consumption is 2.6 mW. The programmable frequency divider based on the P/S counter consists of an 8/9 dual mode divider and a programmable pulse swallow counter. The 8/9 dual-mode frequency divider consists of a synchronous 4/5 divider and an asynchronous divide-by-2. The operating frequency range is 10 GHz to 27 GHz,the minimum input amplitude is 300 mV,and the lowest power consumption is 1.6 m V. The programmable swallow counter uses an improved TSPC D flip-flop with a set-up function with a maximum operating range of 25 GHz and a minimum power consumption of 363 μW. The high-speed programmable multi-mode frequency divider designed in this paper can achieve a frequency division ratio of 32 - 2062;when operating at 28 GHz,the phase noise is lower than-159 dBc/Hz. Dynamic power consumption is 5.2 mW.