数字音频广播基带解码芯片后端设计中的时序收敛方案

在数字集成电路设计中,时序收敛是保证芯片性能的关键,但随着集成电路制造工艺的不断发展,芯片规模不断增加,结构日趋复杂,时序收敛的难度也逐渐加大。该文针对数字音频广播基带解码芯片的后端设计,分析了造成时序违例的原因,并在综合、布图规划、布局等阶段提出了对应的时序收敛策略,最终使芯片满足了系统的时序要求。

Timing Closure in Backend Design of Digital Audio Broadcast Decode Baseband

In digital circuit design,the key to ensure the function of a chip is timing closure,with the development of the process technology,the scale of the chip continue growing,and the configuration becomes more complexity,therefore implementation of timing closure is more and more difficult.For ASIC design of Digital Audio Broadcasting baseband IC,analyses the reason of timing violation first,then propose the relative strategies in synthesis,floorplan,placement etc,the proposed strategies enabled baseband IC to meet timing requirement of the system at last.