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H.264整数DCT的硬件实现
引用本文:韩佳琦,刘瑶,卢化晓.H.264整数DCT的硬件实现[J].电子质量,2012(2):47-49.
作者姓名:韩佳琦  刘瑶  卢化晓
作者单位:重庆邮电大学光电工程学院,重庆,400065
摘    要:该文在分析了H.264整数DCT(Discrete Cosine Transform)变换原理的基础上,介绍了一种实现4×4前向整数变换的新算法。该算法较多地运用了矩阵运算,与传统的将一个二维DCT变换转变为两个一维DCT变换相比,省略了转置模块,降低了时钟延时,减少了资源占用,更利于达到基于H.264的视频信号处理的性能要求。根据新的算法编写了verilog程序并在QuartusⅡ8.0软件中进行了仿真并得出结果。

关 键 词:H.264  DCT  FPGA  整数变换

A Hardware Implementation of Integer DCT in H.264
Han Jia-qi,Liu Yao,Lu Hua-xiao.A Hardware Implementation of Integer DCT in H.264[J].Electronics Quality,2012(2):47-49.
Authors:Han Jia-qi  Liu Yao  Lu Hua-xiao
Affiliation:(College of Electroning Engineering,Chongqing University of Posts and Telecommunications,Chongqing 400065)
Abstract:In this paper,the principle of the integer DCT in H.264 is analyzed and then a new algorithm for realization of 4×4 forward integer transform is introduced.There is much a lot of operation of matrix in this algorithm.Compared with the traditional method of decomposing a 2-dimentional DCT transform into two 1-dimentional DCT transforms,the new one doesn't need transpose module,makes the clock cycle delay lower and uses less resources in FPGA,which is more suitable for video signal processing based on H.264.According to the new algorithm,the Verilog program is written and run in QuartusⅡ8.0.
Keywords:H  264  DCT(Discrete Cosine Transform)  FPGA(Field-Programmable Gate Array)  integer transform
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