基于FPGA和EPP的芯片测试电路设计

提出了一种基于FPGA和EPP并口的模数转换器芯片测试电路设计。通过FPGA实现了对待测试芯片的数据读出和控制,并将数据进行相关处理,再通过EPP并口模块与计算机系统连接,实现了待测试芯片与计算机的双向通信,其通信速率达到1.2MB/s。在介绍芯片测试电路各个模块电路的基础上,详细讲述了测试芯片所集成的2种模数转换器电路、信号处理电路以及EPP并口的功能及实现原理。本设计已经应用于实际的芯片测试系统中,其性能良好,工作稳定,达到了预期的设计目标。

A Design of Chip Test Circuits Based on FPGA and EPP

A circuit design based on Field Programmable Gate Array(FPGA)and Enhanced Performance Profiles(EPP)for Analog-to-Digital Converter(ADC)chip test system is presented in this paper.The ADC chip is controlled by the FPGA,the data is read out and processed through the FPGA,and the FPGA is connected with the personal computer system by the EPP part,then bidirectional communication is realized between the PC and the ADC chip,and the communication data rate is up to 1.2 Mb/s.The paper describes in detail the function and the implementation principle of the two integrated ADC circuits of the test chip,the signal processing circuit and EPP based on the introduction to every module circuit of the chip testing circuit.This proposed design has been used in practical chip test system,and the result of the implementation shows that it has a superior performance and achieves the desired goal.