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Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs |
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| Authors: | Nazanin Mansouri Ranga Vemuri |
| Affiliation: | (1) Digital Design Environments Laboratory, ECECS Department, University of Cincinnati, Cincinnati, Ohio 45221-0030, USA;(2) Digital Design Environments Laboratory, ECECS Department, University of Cincinnati, Cincinnati, Ohio 45221-0030, USA |
| Abstract: | |
| Keywords: | correctness conditions high-level synthesis RT-level verification formal synthesis theorem proving |
| 本文献已被 SpringerLink 等数据库收录！ | |
