网络处理器数据处理内核的设计与实现

通用处理器和专用芯片ASIC的数据处理能力无法满足日益增长的网络带宽和各种复杂网络协议的要求，针对该问题，研究网络处理器的系统结构，讨论网络处理器中数据处理内核的设计实现，提出一种可编程的精简指令集计算机(RISC)处理器微结构，对其进行现场可编程门阵列(FPGA)原型验证，结果证明了该设计方案的有效性。

Design and Realization of Data Processing Core in Network Processor

Data processing capability of General Purpose Processor(GPP) and Application Specific Integrated Circuit(ASIC) can not meet the requirements of increasing network bandwidth and complex protocols, so that this paper researches the architecture of Network Processor(NP), discusses the design and realization of data processor core in network processor, and proposes a programmable Reduced Instruction Set Computer(RISC) micro-architecture of processor. It demonstrates the feasibility of design scheme through Field Programmable Gate Array(FPGA) prototype.