(英) 基于石英基片工艺的D频段平衡式二倍频器设计

设计了一款D频段基于商用平面肖特基二极管DBES105a以及石英基片的二倍频器.通过对传统的用于平衡式混频器及倍频器的鳍线/悬置微带线巴伦耦合器进行改进,提出了一种方便为肖特基二极管外加偏置的平衡式倍频结构.首先,提出了一种适用于石英基片的波导/鳍线过渡结构,并且通过仿真及实验对该结构进行了验证,测试结果表明,这种过渡结构的损耗只有0.15 dB.在驱动功率为26.3 mW、外加反偏电压为0.4 V时,倍频器的测试最大输出功率为3.39 mW,对应倍频效率为12.9%.在外加偏置电压偏离最佳偏置点时,倍频器的输出功率从3.1mW降低到2.0 mW.这也说明:为了达到最大倍频输出功率,也需要为肖特基变阻二极管倍频器提供外加直流偏置.

Design of a D-band balanced frequency doubler with quartz substrate

A D-band frequency doubler with quartz substrate is proposed in this paper with commercial planar Schottky diodes DBES105a. The balun in the doubler is implemented by finline-suspended-stripline coupler (FSSC). The waveguide-to-finline transition suit for quartz substrate has only 0.15 dB measured insertion loss. Compared with traditional coupler in balanced doubler and mixer designs, it has the advantage of easier bias for the diodes. Measured results of the doubler showed that the maximum output power is 3.39 mW with 0.4 V reverse bias voltage and 26.3 mW drive power. Its corresponding peak efficiency is 12.9%. The output power of the doubler is reduced from 3.1 mW to 2.0 mW when the bias voltage deviates from its optimum bias condition. The finding shows that proper external DC bias for Schottky varistor multiplier is as important as for schottky varactor diode frequency multiplier.