Estimating the sustainable capacity of semiconductor fab workstations |
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Authors: | James P Ignizio |
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Affiliation: | 1. Department of Manufacturing Engineering , University of Texas-Pan American , Edinburg, Texas 78539-2999, USA igniziojp@utpa.edu |
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Abstract: | The cost of a semiconductor wafer fabrication facility (i.e. ‘fab’) may be as much as five or more billion US dollars. As such it is essential to determine the capacity (e.g. in terms of ‘wafer starts per week’) of such facilities. An accurate estimate of capacity – under real world conditions – is, however, difficult to achieve. Furthermore, the method for the computation of the capacity of a semiconductor fab is significantly different from that for the capacity of workstations in more conventional, less complex factories. This is due in part to the reentrant nature of the workstations (a.k.a. ‘toolsets’) that comprise a fab's production line as well as the ubiquitous employment of operation-to-machine dedications (a.k.a. layer-to-tool qualifications) – plus the need to consider multiple products employing, perhaps, a different sequence of processing steps. In this article, the matter of workstation capacity, in general, and semiconductor fabs, in particular, is examined. A means to quickly and effectively determine the maximum theoretical capacity of a workstation is developed and illustrated – followed by a way in which the more practical maximum sustainable capacity may be estimated. |
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Keywords: | semiconductor fab computer chips semiconductor wafer fabrication capacity cycle time optimisation |
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