低电压SRAM测试电路设计与实现

本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现，重点研究低电压SRAM的故障模型和测试算法，并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分，前者针对稳定性故障有着良好的覆盖率，后者在传统March C+算法基础上，提出了一种新的测试算法，March-Like算法，该算法能够实现更高的故障覆盖率。仿真结果表明，本文设计的DFT电路能够减小稳定性故障的最小可检测电阻，提高了稳定性故障的测试灵敏度；March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。

Design and Implementation of Low Voltage SRAM Built-In Self-Test Circuit

Based on SMIC 40nm LL CMOS technology, the test circuit of a 256Kb low voltage 8T SRAM chip is designed and implemented in this paper. The fault model and test algorithm of low voltage SRAM are focused on, and the simulation and analysis are completed. The circuit includes two parts, DFT circuit and built-in self-test circuit. The former has good coverage for stability faults. On the basis of traditional March C+ algorithm, the latter proposes a new test algorithm--March-Like algorithm, which can achieve higher fault coverage. The simulation results show that the DFT circuit designed in this paper can reduce the minimum detectable resistance of the stability fault and improve the test sensitivity of the stability fault. The March-Like algorithm can detect the write destructive coupling faults, read destructive coupling faults and write disturb faults in the low voltage SRAM array.