5 V, 8 bit, 100 MS/s fully differential CMOS sample-and-holdamplifier

A 5 V, 100 MS/s fully differential CMOS sample-and-hold amplifier (SHA) with 8 bit accuracy is proposed. Based on the stability limitations of closed-loop SHAs studied in a previous paper (see Int. J. Electron., vol. 78, no. 5, p. 907-910, 1995), the proposed SHA is implemented by an open-loop structure using the `gain-enhanced unity-gain amplifier' to avoid the stability problem and achieve higher operation speed. Simulation results which agree well with experimental results have been obtained to demonstrate the accuracy of the proposed circuit