Analysis for optimum threshold voltage and load current of E-D-type GaAs DCFL circuits |
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| Authors: | Ino M Hirayama M Ohmori M |
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| Affiliation: | NTT, Musashino Electrical Communication Laboratory, Musashino, Japan; |
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| Abstract: | A GaAs MESFET E-D invertor was analysed to estimate the optimum threshold voltage VT for a switching FET, and the optimum load current IL for a load FET, that will minimise the invertor switching time. The calculated results show that the optimum VT lies at around 0.2 V, and the optimum IL is about 55% of the saturation current of the switching FET. |
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