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A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning methodfor DLL replica |
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| Authors: | Kuge S Kato T Furutani K Kikuda S Mitsui K Hamamoto T Setogawa J Hamade K Komiya Y Kawasaki S Kono T Amano T Kubo T Haraguchi M Nakaoka Y Akiyama M Konishi Y Ozaki H Yoshihara T |
| Affiliation: | ULSI Dev. Centre, Mitsubishi Electr. Corp., Hyogo ; |
| Abstract: | A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation |
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