| 基于Avalon总线的PID控制器的硬件实现 |
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| 引用本文： | 潘峥嵘,张赵良,朱菊香.基于Avalon总线的PID控制器的硬件实现[J].微计算机应用,2008,29(12). |
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| 作者姓名： | 潘峥嵘 张赵良 朱菊香 |
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| 作者单位： | 1. 兰州理工大学,电气工程与信息工程学院,兰州,730050
2. 江南大学,信息与控制工程学院,无锡,214100 |
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| 摘 要： | 提出了一种数字PID控制器在FPGA上的硬件实现方法。详细阐述了3级并行流水线结构的PIDIP核的原理和实现方法,介绍了FPGA内部互联各片内设备的Avalon总线。控制器在在CycloneII系列的EP2C5F256C6上实现,实验表明,这种PID控制器在具备高速性的同时还具有很高的可重用性,并更易于调试和实现多通道控制。
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| 关 键 词： | PID控制 Avalon片内总线 |
Hardware Implementation of a PID Controller Based on Avalon Bus |
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| PAN Zhengrong,ZHANG ZhaoLiang,ZHU JuXiang.Hardware Implementation of a PID Controller Based on Avalon Bus[J].Microcomputer Applications,2008,29(12). |
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| Authors: | PAN Zhengrong ZHANG ZhaoLiang ZHU JuXiang |
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| Abstract: | This paper presents a hardware implementation of a digital PID Controller.The PID IP core which has a three level parallel pipelining and the Avalon bus that the FPGA connect in chip devices are described detailed.This PID controller is put in practice in Cyclone II EP2C5F256C6.It is proved that the new PID controller has features of high speed and high reuse ability.Further more,it is easy to debug and achieve multiple channels control. |
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| Keywords: | FPGA SOPC |
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