| 基于DDS＋PLL一种快速跳频频率合成电路的设计与实现 |
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| 引用本文： | 王战永.基于DDS＋PLL一种快速跳频频率合成电路的设计与实现[J].移动通信,2014(24):57-61. |
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| 作者姓名： | 王战永 |
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| 作者单位： | 中国电子科技集团公司第七研究所,广东广州510310 |
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| 摘 要： | 通过介绍DDS＋PLL的工作原理,综合利用PLL和DDS的优缺点,提出了扫频源频率合成电路设计方案。主要针对具体电路的设计与实现方法进行详细阐述,给出了相应测试数据,并对相关问题进行了分析。
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| 关 键 词： | 频率合成 DDS PLL AD9956 |
Design and Implementation of Fast Hopping Frequency Synthesizer Based on DDS and PLL |
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| WANG Zhan-yong.Design and Implementation of Fast Hopping Frequency Synthesizer Based on DDS and PLL[J].Mobile Communications,2014(24):57-61. |
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| Authors: | WANG Zhan-yong |
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| Affiliation: | WANG Zhan-yong (China Electronics Technology Group Corporation No,7 Research Institute, Guangzhou,10310, China) |
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| Abstract: | By introducing the principles of direct digital synthesizer（DDS） and phase locked loop（PLL）, a design scheme of sweep source frequency synthesis circuit is presented based on the advantages and disadvantages of PLL and DDS in this paper. The detailed circuit design and its implementation are expounded. Test data results are given and corresponding debug is analyzed. |
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| Keywords: | frequency synthesis DDS PLL AD9956 |
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