基于eFPGA 的通信基带加速器的逻辑重构设计

为解决CMOS器件特征尺寸缩小带来的SoC(System on Chip,片上系统)芯片可靠性失效的问题,提出了一种基于eFPGA(embedded FPGA,嵌入式FPGA)的在线编程功能实现故障电路逻辑重构的方法。对eFPGA技术优势、JTAG(Joint TestAction Group,联合测试工作组协议)工作原理进行了分析,选取通信基带信号处理的典型算法：FFT(Fast Fourier Transform,快速傅里叶变换)、FIR(Finite Impulse Response,有限脉冲响应)滤波算法为例,模拟通信基带加速器功能失效时,借助JTAG技术配置新的互连关系,利用eFPGA进行逻辑重构,替代通信基带加速器结构实现功能自愈。仿真及验证结果显示eFPGA在面积与功耗方面具备优势,此方案可以实现预期逻辑重构的功能,能有效提高系统可靠性与灵活性。

Logic reconfiguration design of communication baseband accelerator based on eFPGA

In order to solve the problem of SoC reliability failure caused by feature size reduction of CMOS devices, a scheme which realize logic reconfiguration of fault circuit based on online programming function of eFPGA is proposed. The technical advantages of eFPGA and the working principles of JTAG areanalyzed. The typical communication baseband signal processing algorithms, such as FFT algorithm and FIR filtering algorithm, are selected as example to simulate the logic reconfiguration when communication baseband accelerator function fails. JTAG technology is used to reconfigure the interconnection, therefore the eFPGA replaces the structure of communication baseband accelerator to realize function self-healing. Simulation and verification results show that eFPGA has advantages in area and power consumption. This scheme can achieve the expected logic reconfiguration function and effectively improve the reliability and flexibility of system.