应用于JPEG2000的离散小波变换并行VLSI结构

针对离散小波变换硬件资源占用率高的问题，提出了一种应用于JPEG2000的离散小波变换并行VLSI结构；引入了基于时间差的(9,7)小波并行滤波技术，使行和列滤波器同时进行滤波；采用2×2转置模块，实现了几个寄存器代替大量的中间转置存储空间。实验结果表明，该结构在关键路径的约束条件下，有效降低了硬件复杂性，大大提高了硬件资源利用率，几乎达到100%。该结构已通过VHDL 布局布线后仿真验证，并可作为单独的IP核应用于正在开发的VDR雷达图像采集卡中。

Parallel VLSI architecture of discrete wavelet transform for JPEG2000

In order to solve the problem that the VLSI architecture of discrete wavelet transform wastes a huge amount of hardware resources, we propose a parallel VLSI architecture of discrete wavelet transform for JPEG2000. The architecture introduces (9,7) wavelet parallel filtering technique based on the time difference, so that the row processor and the column processor can process the signals in parallel way. The 2×2 transforming module makes it true that several registers substitute a lot of medium transforming memory. Experimental results show that the proposed architecture, under the tight critical path, can efficiently decrease the hardware complexity and achieve hardware utilization nearly 100%. Finally, the architecture has been implemented in post-route VHDL, and can be used as a compact and independent IP core for VDR radar image acquisition card.