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Low power and high speed design issues of CMOS Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor |
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| Authors: | Bari Surajit De Debashis Sarkar Angsuman |
| Affiliation: | 1.ECE Department, Narula Institute of Technology, Kolkata, India ;2.Department of Computer Science and Engineering, Maulana Abul Kalam Azad University of Technology, West Bengal, Salt Lake, Kolkata, West Bengal, India ;3.ECE Department, Kalyani Government Engineering College, Kalyani, Nadia, West Bengal, India ; |
| Abstract: | Microsystem Technologies - This paper represents low power and high speed design issues of Hamming code generation and error detection circuit using complementary metal oxide semiconductor (CMOS)... |
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