| Partition-based Low Power DFT Methodology for System-on-chips |
| |
| 作者姓名： | 李宇飞 陈健 付宇卓 |
| |
| 作者单位： | School of Microelectronics, Shanghai Jiaotong University, Shanghai 200030, China |
| |
| 基金项目： | 国家高技术研究发展计划(863计划) |
| |
| 摘 要： | This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.
|
| 关 键 词： | 片上系统 分区 DFT方法论 功率耗散 |
| 文章编号： | 1672-5220（2007）01-0017-06 |
| 修稿时间： | 2005-03-07 |
Partition-based Low Power DFT Methodology for System-on-chips |
| |
| LI Yu-fei,CHEN Jian,FU Yu-zhuo.Partition-based Low Power DFT Methodology for System-on-chips[J].Journal of Donghua University,2007,24(1):17-22. |
| |
| Authors: | LI Yu-fei CHEN Jian FU Yu-zhuo |
| |
| Affiliation: | School of Microelectronics, Shanghai Jiaotong University, Shanghai 200030, China |
| |
| Abstract: | This paper presents a partition-based Design-forTest (DFT) technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to Iow power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation(EDA) tools from Synopsy(s) to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-on-chips (SOC). The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test in ADVANTEST. |
| |
| Keywords: | DFT partition fault coverage power dissipation IP scan domain |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
