自适应二进制算术编码的动态可重构实现研究

针对H.266/VVC视频编码标准下的上下文自适应二进制算术编码器编码速度慢、资源开销大的问题，面向可重构结构依据算法的内在并行特性优化了编码架构，并基于动态可重构阵列处理器设计实现了CABAC编码器常规编码模式下的并行映射方法，阵列结构能够根据编码输入对优化后的算法进行动态重构，在避免专用硬件编码器较高的资源开销情况下利用软件重构的方法实现熵编码过程，保证编码准确性的同时提高了视频数据流编码效率，为此类运算密集型算法的硬件实现提供了更为灵活高效的参考途径。仿真结果表明，映射实现的编码过程中每个编码周期完成5个二进制序列的编码，平均编码效率达到384.13Mbin/s。基于FPGA的测试结果表明，软件重构方法与专用硬件实现的编码器相比，资源开销降低且编码效率提升5.47%，与同类型可重构视频编码结构相比，编码效率提升7.03%。

Research on dynamic reconfigurable implementation of context adaptive binary arithmetic coding

In response to the slow coding speed and high resource overhead of the Context-based adaptive binary arithmetic coding under the H.266/VVC video coding standard, the reconfigurable oriented architecture optimized the coding architecture based on the intrinsic parallelism of the algorithm, and designs and implements a parallel mapping method for the CABAC encoder in conventional coding mode based on a dynamically reconfigurable array processor. The array structure is able to dynamically reconfigure the optimized algorithm according to the coding input, and the software reconfiguration method is used to implement the entropy coding process without the high resource overhead of dedicated hardware encoders. Simulation results show that the mapped encoding process completes five binary sequences per encoding cycle with an average encoding efficiency of 384.13Mbin/s. FPGA based test results show that the software reconstruction approach reduces the resource overhead and improves the encoding efficiency by 5.47% compared to dedicated hardware implementations, and improves the encoding efficiency by 7.03% compared to similar reconfigurable video encoding structures.