Verification and revision of the power-down mode for hierarchical analog circuits |
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| Affiliation: | 1. Sharif University of Technology, Kish Island International Campus, Department of Engineering and Science, Iran;2. Karlsruhe Institute of Technology (KIT), Computer Science Faculty, Karlsruhe, Germany;3. Sharif University of Technology, Department of Computer Engineering, Tehran, Iran;1. Infineon Technolgies, Neubiberg, Germany;2. Technische Universität München, München, Germany;3. Fraunhofer EMFT, München, Germany;4. Raith GmbH, Dortmund, Germany;1. College of Information Engineering, Wuhan University of Technology, 430070, Wuhan, China;2. Huawei Technologies Co., Ltd., 430070, Wuhan, China |
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| Abstract: | Specialized power-down circuitry can switch off an analog circuit when not required for system operation. When interconnecting sub-circuits with power-down functionality, new design errors, i.e. short-circuit paths, floating nodes and asymmetrical voltages at matched structures, may emerge in the power-down mode of the resulting hierarchical circuit. This paper presents a new method for the verification of the power-down mode of hierarchical analog circuits. In contrast to flat verification approaches, intermediate results are reused during computation. The obtained verification results can be used to revise and correct detected errors. Experimental results for a high input impedance differential amplifier are given. |
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| Keywords: | Analog circuits Power-down mode Hierarchical circuits Matching Symmetries Short-circuit paths Floating nodes |
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