| 基于DSP和FPGA的HDLC协议通讯电路设计 |
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| 引用本文： | 刘岩俊,闫海霞,魏仲慧.基于DSP和FPGA的HDLC协议通讯电路设计[J].电子测量技术,2009,32(6):137-139. |
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| 作者姓名： | 刘岩俊 闫海霞 魏仲慧 |
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| 作者单位： | 1. 中国科学院长春光学精密机械与物理研究所,长春,130033
2. 吉林大学电子学院,长春,130012 |
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| 摘 要： | 为了实现高速HDLC通讯协议，设计了DSP＋FPGA结构的485通讯接口，接口包括DSP、FPGA、485转换等硬件电路，以及DSP与FPGA之间的数据交换程序和FPGA内部状态机；其中DSP用于实现数据控制，FPGA用于实现HDLC通讯协议，DSP与FPGA之间采用XINTF方式，通过双FIFO缓存进行数据交换。通过PCI接口连接PC机对系统进行测试，测试结果表明，系统通讯速度为1Mbps，并且工作稳定。
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| 关 键 词： | HDLC RS485 FPGA DSP |
Design of HDLC protocol communication circuit based on DSP and FPGA |
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| Liu Yanjun,Yan Haixia,Wei Zhonghui.Design of HDLC protocol communication circuit based on DSP and FPGA[J].Electronic Measurement Technology,2009,32(6):137-139. |
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| Authors: | Liu Yanjun Yan Haixia Wei Zhonghui |
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| Affiliation: | Liu Yanjun, Yan Haixia, Wei Zhonghui(1. Changehun Institute of Optics, Fine Mechanics and Physics, the Chinese Academy of Sciences, Changehun 130033; 2. JiLin University Eleetronie Department, Changehun 130012) |
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| Abstract: | In order to realize the high speed HDLC communication protocol, a 485 interface with DSP ＋ FPGA is designed, the interface includes the hardware circuit of DSP, FPGA, 485 conversion, the program of data exchange, and state machine. DSP control the communication data, FPGA implement the HDLC protocol, The FPGA and DSP exchange data with two FIFO cache by XINTF interface. The system is tested by PC with PCI interface, experiments results show that the interface works stable with 1 Mbps speed. |
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| Keywords: | HDLC RS485 FPGA DSP |
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