一种部分流水的多塔三维SoC测试时间优化算法

针对硬晶片构成的多塔三维SoC绑定中测试，提出考虑测试访问机制、层间硅通孔数和测试功耗约束的测试时间优化算法。只要任意一种测试资源约束不满足待调度晶片测试，就依次释放最早结束测试的晶片测试资源，直到待调度晶片尽可能提前测试为止，以此实现该晶片与未结束测试晶片的部分流水。选用ITC02测试基准电路中的5种典型电路，手工搭建2种塔内包含子塔的多塔三维SoC。实验结果表明，与已有算法相比，提出的算法减少了空闲时间块，显著缩短了总测试时间；实验还发现，与增加TSV数相比，增大测试引脚数更能有效减少多塔三维SoC的总测试时间。

A test time optimization algorithm for multi-tower 3D SoCs based on partially pipelined test

Aiming at the mid-bond test of hard-die based multi-tower 3D SoCs, this paper proposes a novel test time optimization algorithm considering the test resource constraints such as test access mechanism, Through-Silicon-Via count, and test power consumption. Once any remaining test resources do not satisfy the requirements of the die to be scheduled for testing, the test resources for the die that ends testing the earliest are released, until the die to be scheduled can be tested ahead of time as much as possible, thus obtaining partially pipelined testing between the newly scheduled die and the unfinished die. Five typical circuits in the ITC02 test benchmark circuit were selected, and two types of multi-tower 3D SoCs containing sub-towers were manually constructed. The results show that, compared with the existing algorithms, the proposed algorithm reduces the idle time blocks and significantly shortens the total test time. In addition, compared with increasing the number of TSVs, increasing the number of test pins can effectively reduce the total test time of a multi-tower 3D SoC.