A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities

This paper presents the design and the implementation of a coarse-grain reconfigurable machine used as an accelerator for a programmable RISC core, to speed up the execution of computationally demanding tasks like multimedia applications. We created a VHDL model of the proposed architecture and implemented it on a FPGA board for prototyping purposes; then we mapped on our architecture some DSP and image processing algorithms as a benchmark. In particular, we provided the proposed architecture with subword computation capabilities, which turns out to be extremely effective especially when dealing with image processing algorithms, achieving significant benefits in terms of speed and efficiency in resource usage. To create the configuration bitstream (configware) we created a tool based on a graphical user interface (GUI) which provides a first step towards the automation of the programming flow of our design: the tool is meant to ease the life of the programmer, relieving him from the burden of calculating the configuration bits by hand. Synthesis results indicate that the area occupation and the operating frequency of our design are reasonable also when compared to other similar design. In addition to this, the amount of clock cycles taken by our machine to perform a given algorithm is orders of magnitude smaller than the one required by a corresponding software implementation on a RISC microprocessor.