| 基于MII接口的硬件IP包过滤技术 |
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| 引用本文： | 毛章根,雷鸣,庞磊.基于MII接口的硬件IP包过滤技术[J].计算机安全,2011(10):6-8. |
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| 作者姓名： | 毛章根 雷鸣 庞磊 |
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| 作者单位： | 江南计算所,江苏无锡,214083 |
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| 摘 要： | 针对普通VPN实现机制易受攻击的缺陷,提出了一种基于MII接口的硬件IP包过滤技术.利用物理层芯片Back-to-Back技术,在普通VPN机制中增加硬件IP包过滤模块,切断CPU模块和外网的物理直连,防范外网黑客对VPN设备的CPU操作系统和协议栈的扫描、阻塞等攻击.对比普通VPN实现机制,阐述了改进的VPN逻辑原理...
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| 关 键 词： | 以太网 MII接口 PHY芯片 FFPGA IP包过滤 |
The hardware-IP packet filtering technology based on MII interface |
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| MAO Zhang-gen,LEI Ming,PANG Lei.The hardware-IP packet filtering technology based on MII interface[J].Network & Computer Security,2011(10):6-8. |
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| Authors: | MAO Zhang-gen LEI Ming PANG Lei |
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| Affiliation: | MAO Zhang-gen,LEI Ming,PANG Lei(Jiangnan Institute of Computing Technology,Wuxi,Jiangsu 214083,China) |
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| Abstract: | For VPN vulnerability,this paper presents a hardware IP packet-filtering technology based on MII interface.Use of the physical layer chip Back-to-Back technology,we increase a hardware IP packet-filtering module in VPN,so we can cut off the directly connection between CPU module and WAN,prevent scanning,blocking and other attacks to CPU operating system and protocol stack from hackers of WAN.Through a comparison,this paper explains logical structure of the improved VPN and the main IP packet-filtering proce... |
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| Keywords: | Ethernet MII interface PHY FPGA IP packet filtering |
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