一种简易数字信号传输性能分析仪的设计

采用FPGA作为数字信号发生器,利用线性移位寄存器产生要求的M序列,作为数字信号以及模拟信道噪声信号。利用单片机（MSP430FG4618）产生不同的频率,控制M序列时钟,从而改变数据率。采用集成滤波器芯片LT1568,通过改变外围电阻,实现不同的截止频率,模拟信道幅频特性。信号分析电路采用低通滤波器降低信号噪声。同步...

Design of a Simple Digital Signal Transmission Performance Analyzer

The system uses the FPGA as digital signal generator,in which a linear shift register generates the M sequence,as the digital signal to be transmitted and simulated channel noise.Using SCM（MSP430FG4618）,this paper gets different frequency signals to control the clock of the M sequence,thus changing the data rate.Integrated filter chip,LT1568,simply by changing its external resistor to get different cut-off frequencies,is used to shape channel amplitude-frequency characteristics and a low pass filter is used to reduce signal noise.When synchronous clock is available,it can be used directly as synchronous scanning signal connected to the external trigger of oscilloscope.Meanwhile,the digital signal after filtering is connected to oscilloscope and steady eye patterns can be observed.When synchronized clock is not available,we extract synchronized clock form the transmitted digital signal firstly,and then generate synchronous scanning signal that triggers display of eye patterns.