| 单片机总线上多时钟域下数据传递的可靠性研究 |
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| 引用本文： | 杨莉,舒军,焦启民.单片机总线上多时钟域下数据传递的可靠性研究[J].湖北大学学报(自然科学版),2009,31(1):39-43. |
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| 作者姓名： | 杨莉 舒军 焦启民 |
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| 作者单位： | 杨莉,焦启民,YANG Li,JIA Qi-min(湖北第二师范学院,计算机科学与工程系,湖北,武汉,430205);舒军,SHU Jun(湖北工业大学,电气与电子工程学院,湖北,武汉,430068)
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| 基金项目： | 湖北省教育厅优秀中青年人才基金 |
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| 摘 要： | 对单片机总线上多时钟域下数据传递的可靠性进行研究，阐述了使用寄存器锁存电路、多级锁存电路2种方法解决多时钟域下数据传递可靠性时存在的问题，提出了采用4级锁存并判断跳变沿的方式能确保多时钟域下数据可靠传递的方法，具有很高的应用价值．
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| 关 键 词： | 多时钟域 异步电路设计 亚稳态 |
Reliability of data transfer in multiple-clock-domain on single chip microcontroller bus |
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| YANG Li,SHU Jun,JIAO Qi-min.Reliability of data transfer in multiple-clock-domain on single chip microcontroller bus[J].Journal of Hubei University(Natural Science Edition),2009,31(1):39-43. |
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| Authors: | YANG Li SHU Jun JIAO Qi-min |
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| Affiliation: | 1.Department of Computer Science and Engineering;Hubei University of Education;Wuhan 430205;China;2.Institute of Electrical and Electronic Engineering;Hubei University of Industrial;Wuhan 430068;China |
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| Abstract: | The reliability of data transfer was studied in multiple-clock-domain on single chip microcontroller bus.The deficiencies of two methods,register clock out circuit and multi-level lock out circuit,which used to promote the data transfer reliability in multiple-clock-domain,were described.The four-level lock out circuit and an edge trigger circuit method was put forward,and the results were shown that it was able to guarantee reliable data transfer and this method was high practical. |
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| Keywords: | multiple clock domain asynchronous circuit design metastability |
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