一种高速FIR数字滤波器的VLSI设计与实现

讨论了一种快速的FIR数字滤波器在VLSI中实现的设计方法.采用基于快速滤波算法(FFAs)的并行滤波器结构,提高了滤波器的工作速度;并结合算法强度缩减技术,降低了硬件面积占用和功率消耗.实验结果表明,采用这种方法可以灵活处理综合的硬件面积占用和速度的约束关系,使设计达到最优.该方法适用于高速和硬件面积要求下的数字滤波模块的VLSI实现.

On a Design of High - speed FIr Digital Filter in VLSI

In this paper, a VLSI design method for high - speed FIR digital filter is presented. The FIR digital filter adopts a parallel filter architecture based on fast FIR algorithms(FFAs) , improving the filter speed. In addition, the architecture is combined with algorithmic strength reduction to reduce hardware overhead and power consumption. Experiments show that the area and speed restriction of the synthesis can be flexibly optimized by using the improved algorithm of the proposed FIR filter architecture. The method can be used as VLSI realization of digital filter module wit highspeed and hardware - overhead.