| 高速网络安全协处理器中PCI-X接口设计 |
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| 引用本文： | 朱莹,白国强,陈弘毅.高速网络安全协处理器中PCI-X接口设计[J].计算机工程,2009,35(7):212-214. |
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| 作者姓名： | 朱莹 白国强 陈弘毅 |
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| 作者单位： | 清华大学微电子学研究所信息科学与技术国家实验室,北京,100084 |
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| 基金项目： | 国家自然科学基金，国家高技术研究发展计划(863计划) |
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| 摘 要： | 介绍高速网络安全协处理器中PCI-X接口模块的设计方法，利用IPSec和SSL／TLS2种协议优化系统，并配置各种算法引擎。协处理器采用具有更高性能的PCI-X总线接口及SoC芯片，能够同时满足PCI-X总线协议和协处理器内部的特殊传输要求。实验结果表明，该设计方法是可行的。
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| 关 键 词： | PCI-X总线接口 密码安全 协处理器 |
Design of PCI-X Interface for High Speed Network Security Co-processor |
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| ZHU Ying,BAI Guo-qiang,CHEN Hong-yi.Design of PCI-X Interface for High Speed Network Security Co-processor[J].Computer Engineering,2009,35(7):212-214. |
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| Authors: | ZHU Ying BAI Guo-qiang CHEN Hong-yi |
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| Affiliation: | National Lab of Information Science & Technology;Institute of Microelectronics;Tsinghua University;Beijing 100084 |
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| Abstract: | The method to design PCI-X interface for high speed network security co-processor is introduced, which uses two protocols such as IPSec and SSL/TLS protocols to optimize the system, and deploys different kinds of algorithm engines.The co-processor uses PCI-X bus interface and SoC chip with higher performance, which meets the requirement of both PCI-X bus protocol and the internal data transfers of co-processor.Experimental results show this method is feasible. |
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| Keywords: | PCI-X bus interface cipher security co-processor |
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