| 1．8V高电源抑制比的CMOS带隙基准电压源 |
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| 引用本文： | 方穗明,王占仓,高风.1．8V高电源抑制比的CMOS带隙基准电压源[J].北京工业大学学报,2007,33(10):1052-1055. |
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| 作者姓名： | 方穗明 王占仓 高风 |
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| 作者单位： | 北京工业大学,电子信息与控制工程学院,北京嵌入式系统重点实验室,北京,100022 |
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| 摘 要： | 通过对电压源传统设计中关于速度、噪声、工作温度范围方面的研究,设计了一种带隙基准电压源.基于TSMC工艺套件的电路模拟仿真表明,该电路可在1.5～1.8V电压下正常工作,功耗小于0.5 mW,输出电压为1.25V,温度系数低于1.8×10~(-5)/℃,且低频下PSRR的值可以达到-110 dB.
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| 关 键 词： | CMOS 带隙基准电压源 工作温度范围 电源抑制比 温度系数 |
| 文章编号： | 0254-0037（2007）10-1052-04 |
| 修稿时间： | 2006-09-11 |
A 1.8 V CMOS Bandgap Voltage Reference With High Power Supply Rejection Ratio |
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| FANG Sui-ming,WANG Zhan-cang,GAO Feng.A 1.8 V CMOS Bandgap Voltage Reference With High Power Supply Rejection Ratio[J].Journal of Beijing Polytechnic University,2007,33(10):1052-1055. |
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| Authors: | FANG Sui-ming WANG Zhan-cang GAO Feng |
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| Affiliation: | Beijing Embedded System Key Lab, College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing 100022, China |
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| Abstract: | A bandgap voltage reference has been proposed.We have provided improvements on speed,noise, temperature operating range issues compared with traditional bandgap reference design.Validity and accuracy of this scheme are verified by TSMC Process-Design-Kit-Based simulations.Simulation Results proved that this circuit can work at 1.5～1.8 V supply with power consumption less than 0.5 mW,the output reference voltage is 1.25 V,temperature coefficient is less than 1.8×10~(-5)℃and PSRR is-110 dB at DC.This cir- cuit can be widely applied to portable electronic designs. |
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| Keywords: | CMOS |
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