FPGA implementation of fractional-order chaotic systems |
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| Affiliation: | 1. Department of Electronics Engineering, Ramrao Adik Institute of Technology, Nerul, Navi Mumbai 400706, India;2. Department of Electronics and Telecommunication Engineering, Ramrao Adik Institute of Technology, Nerul, Navi Mumbai, India;1. Dept. of Naval Architecture and Marine Engineering, Bandirma Onyedi Eylul University, Bal?kesir, Turkey;2. Dept. of Electrical and Electronics Engineering, Erzincan Binali Yildirim University, Erzincan, Turkey;3. Dept. of Electrical and Electronics Engineering, Istanbul University-Cerrahpa?a, Istanbul, Turkey;1. Data Recovery Key Laboratory of Sichuan Province, College of Mathematics and Information Science, Neijiang Normal University, Neijiang, 641100, China;2. Department of Mathematics, Cankaya University, 06530 Balgat, Ankara, Turkey;3. Institute of Space Sciences, Magurele–Bucharest, Romania;4. College of Water Resource and Hydropower, Sichuan University, Chengdu 610065, China;5. Department of Mathematics, Xiangnan University, Chenzhou 423000, China;1. System on Chip Center (SoCC), Khalifa University of Science and Technology, Abu Dhabi, 127788, United Arab Emirates;2. Nanoelectronics Integrated Systems Center (NISC) Research Center, Nile University, Cairo, Egypt;3. Department of Electrical and Computer Engineering, University of Sharjah, 27272, United Arab Emirates;4. Department of Electrical and Computer Engineering, University of Calgary, Alberta, Canada;5. Department of Computer Science and Engineering, American University of Sharjah, United Arab Emirates;6. Dept. of Mathematica and Physics, Faculty of Engineering, Cairo University, Egypt;1. Department of Applied Mathematics, IPICYT, San Luis Potosi, Mexico;2. Faculty of Electronics Sciences, Benemérita Universidad Autónoma de Puebla, Puebla, Mexico;3. Mathematics Department, University of Houston, Houston, TX 77204-3008, USA;1. School of Electronics and Telecommunications, Hanoi University of Science and Technology, 01 Dai Co Viet, Hanoi, Viet Nam;2. Department of Mechanical and Electrical Engineering, Institute of Mines and Petroleum Industries, University of Maroua, P.O. Box 46, Maroua, Cameroon;3. Department of Physics, Aristotle University of Thessaloniki, Thessaloniki GR-54124, Greece;4. Biomedical Engineering Department, Amirkabir University of Technology, Tehran 15875-4413, Iran;5. Division of Dynamics, Lodz University of Technology, Stefanowskiego 1/15, 90-924 Lodz, Poland;1. University of Patras, Department of Physics, Electronics Laboratory, Patras, Greece;2. University of Sharjah, Department of Electrical and Computer Engineering, Sharjah, United Arab Emirates;3. Nile University, Nanoelectronics Integrated Systems Center (NISC), Giza, Egypt;4. University of Calgary, Department of Electrical and Computer Engineering, Calgary, AB, Canada |
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| Abstract: | This paper presents the digital implementation of fractional-order (FO) chaotic systems on Field Programmable Gate Array (FPGA). In the proposed work Simulink model of each chaotic system is first realized using HDL coder of MATLAB, wherein each coefficient and signal is represented using a fixed number of bits. The construced design is translated into VHDL code using hardware generation block. This code is further translated into bitstream file using Quartus software. The chaotic system is implemented by downloading the obtained bitstream file into Altera FPGA Cyclone IV E (EP4CE11529C7N) chip. A methodology has been developed to construct FO chaotic system using HDL coder. Five different FO chaotic systems, viz., Lorenz, Chen, Lü, Arneodo, and Lorenz Hyperchaotic system have been presented in the paper to illustrate the methodology. The systems have been implemented on FPGA platform. Analysis of each chaotic system is carried out on the basis of hardware resource utilization, static power analysis and synthesis frequency on FPGA. The results show that FPGA provides high-speed realizations with the desired accuracy and low power consumption for FO chaotic systems. |
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| Keywords: | Nonlinear system Chaos Fractional-order chaotic system HDL coder VHDL FPGA implementation |
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