基于FPGA密集假目标干扰的实现

在现代电子战中,应对新体制雷达、雷达干扰机转向采用欺骗性干扰方式,结合DRFM的机理,介绍了可控变间隔的密集假目标产生机理,基于FPGA内部IP核 FIFO 产生密集假目标,通过控制FIFO的存储深度来实现假目标的延迟时间;通过开关控制假目标的输出数量。仿真分析了假目标产生机理的正确性,同时验证了密集假目标产生的硬件可实现性,并给出了硬件实现假目标调幅调频的方法,为相关雷达干扰机硬件实现提供了参考。

Realization of Dense False Targets Jamming Based on FPGA

In modern electronic warfare, radar jammers use deceptive jamming methods for the new radars. Based on the mechanism of DRFM, a detailed introduction is given to the dense false target mechanism of controlled variable interval. False targets are produced based on FPGA IP core internal FIFO, by controlling the depth of FIFO storage to generate the distance deception of false target signal and the transmission number by switch control false target. The validity of the false target mechanism is demonstrated by simulation analysis, and feasibility of the dense false target hardware is verified. A false target to realize hardware arn/fm method is also given to provide reference for related radar jammer hardware implementation.