| 基于UVM验证方法学的AES模块级验证 |
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| 引用本文： | 田劲,王小力.基于UVM验证方法学的AES模块级验证[J].微电子学与计算机,2012,29(8):86-90. |
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| 作者姓名： | 田劲 王小力 |
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| 作者单位： | 西安交通大学微电子学系,陕西西安,710049 |
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| 摘 要： | 分析了基于System Verilog语言的UVM(Universal Verification Methodology)高级验证方法学,并使用该方法学对AES(Advanced Encryption Standard)模块进行了功能验证.验证结果表明,此验证平台能够实时监测覆盖率,控制验证进程,优化验证事务.该方法提高了验证的效率验和证平台的可重用性,较好地满足了芯片验证需要.
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| 关 键 词： | UVM验证方法学 System Verilog AES 随机约束 |
AES Module Level Verification Based on UVM |
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| TIAN Jin,WANG Xiao-li.AES Module Level Verification Based on UVM[J].Microelectronics & Computer,2012,29(8):86-90. |
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| Authors: | TIAN Jin WANG Xiao-li |
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| Affiliation: | (Department of Microelectronics,Xi′an Jiaotong University,Xi′an 710049,China) |
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| Abstract: | This paper analyzed an advanced verification methodology called UVM which based on system verilog language and verified the function of AES.As a result of verification,we can monitor coverage,control the platform and optimize the testbench and testcase.This Methodology can improve the verification efficiency and platform reuse.It well meets the needs of chip verification. |
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| Keywords: | UVM System Verilog AES Random Constraint |
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