A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip |
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| Affiliation: | 1. Quality Semiconductor Australia, Homebush, New South Wales, 2140, Australia;2. Faculty of Informatics, University of Wollongong, Wollongong, New South Wales, 2522, Australia;1. Istanbul Bilgi University, Department of Energy Systems Engineering, Eyüp, Istanbul, Turkey;2. TUBITAK BILGEM, Gebze, Kocaeli, Turkey;1. Department of International Education, The Education University of Hong Kong, Tai Po NT, Hong Kong;2. School of Education, University of Bristol, UK;1. Department of Clinical Epidemiology, Institute of Cardiovascular Diseases and Center of Evidence Based Medicine, The First Affiliated Hospital, China Medical University, Shenyang, China;2. Center of Evidence Based Medicine, Liaoning Province & China Medical University, Shenyang, China |
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| Abstract: | A dynamically reconfigurable bit-serial systolic array implemented in 1.2-μm double-metal P-well CMOS is described. This processor array is proposed as the central computational unit in the Reconfigurable Systolic Array (RSA) neuro-computer and performance estimates suggest that a 64 IC system (containing a total of 1024 usable processors) can achieve a learning rate of 1134 MCUPS on the NETtalk problem. The architecture employs reconfiguration techniques for both fault-tolerance and functionality, and allows a number of neural network models (in both the recall and learning phases) from associative memory networks, supervised networks, and unsupervised networks to be supported. |
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