A 0.5-V low power analog front-end for heart-rate detector |
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Authors: | Naveen Suda P V Nishanth Debajit Basak Durshee Sharma Roy P Paily |
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Affiliation: | 1. Department of Electronics and Electrical Engineering and Centre of Nanotechnology, Indian Institute of Technology, Guwahati, Guwahati, 781039, Assam, India
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Abstract: | This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8–32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply. |
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