一种用于TDC的低功耗多相时钟生成电路

在无人机3D地形测绘中，作为核心模块的时间数字转换器(TDC)需要具有远距离测量能力和高测量分辨率。基于对测距系统的长续航、公里级测距能力和厘米级测量精度的综合考量，文章设计了一种用于TDC的低功耗多相位时钟生成电路。采用了伪差分环形压控振荡器，通过优化交叉耦合结构，在保证低功耗的前提下，提升了信号边缘的斜率，增强了时钟的抖动性能和对电源噪声的抑制能力。在电荷泵设计中，通过对环路带宽的考量选取了极低的偏置电流，在进一步降低功耗的同时缩小了环路滤波器的面积。基于SMIC 180 nm CMOS工艺完成了对多相时钟生成电路的设计。仿真结果表明，在400 MHz的输出频率下，环路带宽稳定在1 MHz。该电路在不同工艺角下均能达到较快的锁定速度，相位噪声为-88 dBc@1 MHz,功耗为1 mW,均方根抖动为27 ps,满足厘米级测距的精度需求。

A Low Power Multi-Phase Clock Generation Circuit for TDC

In UAV 3D terrain mapping, the time-to-digital converter (TDC), which is the core module, needs to have long-range measurement capability and high measurement resolution. Based on the comprehensive consideration of the long range, kilometer-level ranging capability and centimeter-level measurement accuracy of the ranging system, a low power multi-phase clock generation circuit for TDC was designed in this paper. A pseudo-differential ring voltage controlled oscillator was used in this design. By optimizing the cross-coupling structure, the slope of the signal edges was improved, and the jitter performance of the clock and the suppression of power supply noise were enhanced while ensuring low power consumption. In the charge pump design, a very low bias current was selected by considering the loop bandwidth to further reduce power consumption while reducing the area of the loop filter. The multi-phase clock generation circuit was designed in SMIC 180 nm CMOS process. The simulation results show that the loop bandwidth is stable at 1 MHz at an output frequency of 400 MHz. The circuit achieves a fast locking speed at different process corners, with a phase noise of -88 dBc@1 MHz, a power consumption of 1 mW, and a root mean square jitter of 27 ps, meeting the accuracy requirements of centimeter-level ranging.