基于动态目标阻抗的DDR3电源完整性仿真

DDR3存储器已经成为目前服务器和计算机系统的主流应用，虽然DDR3采用双参考电压、片上校准引擎、动态ODT、fly by拓扑以及write leveling等技术在一定程度上提高了信号完整性，但高数据率DDR3的设计实现仍然比较困难。由于DDR3总线属于高速并行总线，同步开关噪声与电源本身的噪声耦合在一起，共同影响数据信号的质量。考虑到芯片实际工作电流并非恒定不变，而是一种动态变化的频率相关源，提出了一种新的基于目标阻抗与动态目标阻抗的混合仿真与设计流程，在前仿真阶段采用恒定目标阻抗，在后仿真阶段采用动态目标阻抗为设计目标，仿真结果证实了该方法的有效性，实现了设计优化速度与精度的权衡折衷。

Simulation on power integrity of DDR3 system based on dynamic target impedance

DDR3 memory has become one of the mainstream applications in current servers and computer systems. Although many techniques such as dual reference voltage, dynamic on die termination (ODT), fly by topology and write leveling, have been adopt by DDR3 in order to improve signal integrity in a certain extent, it is still difficult to design and realize high data rate. Since DDR3 is a typical parallel bus structure, the simultaneous switching noise is couped with the original power noise, affecting the quality of data signals. Taking into account that the chip current is a dynamic changing and frequency related source, the paper proposes a new mixed simulation and design procedure based on target impedance and dynamic target impedance. The constant target impedance is adopted in pre simulation, while the dynamic target impedance is used in post simulation. The trade off between speed and accuracy of design optimization is realized, and simulation results prove the feasibility and efficiency of this method.