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一种新型的针对SRAM-Based FPGAs的容错方法
引用本文:司派发,徐健,黄维康.一种新型的针对SRAM-Based FPGAs的容错方法[J].复旦学报(自然科学版),2001,40(3):326-330.
作者姓名:司派发  徐健  黄维康
作者单位:复旦大学电子工程系CAT室,
基金项目:国家自然科学基金资助项目 (6 97730 11)
摘    要:提出了一种针对基于SRAM型的现场可编程门阵列(FPGA)的新型容错方法,包括一套容错结构以及对应的布线过程,此方法对可编程逻辑单元(CLB)和连线资源的代价都予以考虑,容错布线过程简单,耗时少,模拟结果还显示,该方法与以前的方法比较,具有较低的代价。

关 键 词:现场可编程门阵列  容错布线  容错结构
文章编号:0427-7104(2001)03-0326-05

A Novel Fault Tolerant Approach for SRAM-Based FPGAs
SI Pai fa,XU Jian,HUANG Wei kang.A Novel Fault Tolerant Approach for SRAM-Based FPGAs[J].Journal of Fudan University(Natural Science),2001,40(3):326-330.
Authors:SI Pai fa  XU Jian  HUANG Wei kang
Abstract:A novel fault tolerant approach for SRAM Based FPGAs is presented. The proposed approach includes a fault tolerant architecture and its related routing procedure. In this approach, the overheads for CLBs and interconnects are considered. Under this novel approach the fault tolerant routing procedure is simple and less time consuming. The simulation results show that the proposed approach has lower overhead than previous by published methods.
Keywords:FPGA  fault  tolerant routing  fault  tolerant architecture
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