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A HiperLAN II frame processor implementation
Authors:E P Vasilakopoulou  G D Papadopoulos  G E Karastergios
Abstract:In recent years, wireless access networks offer an alternative method for connecting subscribers to the global communication network. Several high‐speed Wireless LAN's (WLAN) standards have emerged and among them the ETSI BRAN HiperLAN II standard is distinguished for its performance and QoS support. This paper, starting with a short overview of HiperLAN II main features and Medium Access (MAC) protocol, presents the architecture of an implemented high‐speed Frame Processor that realizes the medium access control (MAC) protocol of the HiperLAN II standard. The main goal of the Frame Processor is the real‐time management of the air interface as well as to bridge the upper network layers with the wireless world, relieving the data link control (DLC) layer of time‐consuming tasks such as slot map allocation extraction, bit‐by‐bit processing of data units, framing and synchronization. Copyright © 2003 John Wiley & Sons, Ltd.
Keywords:Wireless ATM  HiperLan II  MAC protocol  framer
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