A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA期刊界 All Journals 搜尽天下杂志传播学术成果专业期刊搜索期刊信息化学术搜索

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

Authors:	Zhang Hui Yang Haigang Wang Yu Liu Fei Gao Tongqiang

Affiliation:	1. Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China;Graduate University of the Chinese Academy of Sciences, Beijing 100049, China 2. Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China

Abstract:	A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partitio...

Keywords:	PLL clock generator reconfigurable VCO
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