基于MCML的高性能三值D型触发器的设计

MCML电路由于具有高速低摆幅、抗干扰能力强、在高频下比传统CMOS电路功耗更低等优点，越来越受到广泛关注.通过分析二值MCML电路的设计方法，引入与参考电压进行比较的思路，设计了一种结构简单的新型高性能三值D型触发器.采用TSMC 180 nm工艺，使用HSPICE进行模拟.结果表明，所设计的触发器不仅具有正确的逻辑功能，工作频率达到10 GHz，平均D-Q延时和PDP也比传统CMOS三值触发器有明显降低，且随着工作频率的上升，PDP不断下降，适合于高速和高工作频率的应用.

Design of high-performance ternary D flip-flop based on MCML

MCML circuits have been paid more and more attention for their high speed, low swing and low noise and its ability of dissipating less power at high frequency than conventional CMOS circuits. Introducing comparison with the reference voltage based on the analysis of binary MCML circuits, a new kind of high-performance ternary D flip- flop based on MCML is proposed, which has simple structure and is completed under the TSMC 180 nm process. The simulations carried out by Hspice prove the proposed circuit has ideal logic function, smaller D-Q delay, lower PDP, and can perform up to 10 GHz frequency. Moreover, the PDP decreases constantly as the working frequency increases. It proves that the proposed circuit is very suitable for high-speed application.