兼容ARM Thumb指令的多指令集处理器技术研究

随着处理器的快速发展，RISC-V的软件生态环境建设成为其在处理器市场中站稳脚跟的关键因素之一。二进制翻译是解决处理器二进制代码兼容性问题、为处理器生态环境建设获取时间成本的关键技术之一，但由于二进制翻译器难以以较低的功耗面积开销获得高效执行的二进制代码，使其无法广泛应用于嵌入式领域。针对二进制翻译器执行效率和功耗面积开销难以取得平衡的问题，采用硬件逻辑加速的方式处理ARMv7-M中条件执行指令、更新标志位指令以及桶形移位指令，并利用静态二进制翻译器对ARMv7-M程序进行IT Block分裂、地址重计算及指令映射后生成RISC-V二进制代码，以此支持ARMv7-M的各类指令。基于开源内核CV32E40P设计了一个支持ARMv7-M的处理器内核，结果表明，运行ARMv7-M程序的平均性能能够达到直接运行RISC-V程序性能的137%，与纯软件二进制翻译支持ARMv7-M相比，该处理器核运行ARMv7-M程序的性能提升了5.59倍。

Research on multi-instruction set processor technology compatible with ARM Thumb instructions

With the development of processors, the construction of a software ecosystem for RISC-V becomes a key factor in securing its position in the processor market. Binary translation technology is one of the crucial technologies for addressing compatibility issues with processor binary code and obtaining time cost for constructing a processor ecosystem. However, binary translators are unable to achieve efficient execution of binary code with low power and area overhead, making them unsuitable for widespread application in the embedded domain. To address the challenge of balancing the execution efficiency and power and area overheads of binary translators, this paper employed hardware logic acceleration to process ARMv7-M conditional execution instructions, updated flag instructions and barrel shift instructions. Then it used static binary translators to split ARMv7-M programs into IT blocks, recalculate addresses, and map instructions to generate RISC-V binary code, supporting all types of ARMv7-M instructions. Based on the open-source CV32E40P kernel, it designed a processor core supporting ARMv7-M, and results show that the average performance of the processor core running ARMv7-M programs can reach 137% of directly running RISC-V programs. Compared with pure software binary translation to support ARMv7-M, the performance of the processor core running ARMv7-M programs improves by 5.59 times.