A low power tunable Gm–C filter based on double CMOS inverters in 0.35?μm

In this article, an inverter based transconductor using double CMOS pair is proposed for implementation of a second order lowpass G_m?CC Filter. The proposed operational transconductance amplifier (OTA) and biquad filter are designed using standard 0.35???m CMOS technology. Simulation results demonstrate the central frequency tunability from 10?kHz to 2.8?MHz which is suitable for the wireless specifications of Bluetooth (650?kHz), CDMA 2000 (700?kHz) and Wideband CDMA (2.2?MHz) applications. The power consumption of the filter is 445?nW and 178???W at 10?kHz and 2.8?MHz from 3.3?V supply voltage, respectively. The active area occupied by the designed filter on the silicon is 215?×?720???m². The proposed approach guarantees the upper bound on THD to be ?40?dB for 300?mVpp signal swing. Employing the double CMOS pair in the inverters causes PSRR to reach 68.6?dB which is higher than similar works.