A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation

This work presents the design of a new and unique design technique of constant loop bandwidth and phase-noise cancellation in a wideband ΔΣ fractional-N PLL frequency synthesizer. Phase noise performance of the proposed ΔΣ fractional-N PLL frequency synthesizer has been verified using CppSim simulator with the help of transistor level simulation results in Cadence SpecctreRF. Transient response of the proposed ΔΣ fractional-N PLL has been verified in transistor level simulation using Cadence SpectreRF in 0.13 μm standard CMOS process. The proposed phase-noise cancellation and constant loop bandwidth in wideband ΔΣ fractional-N PLL reduces the out of band phase noise by 18 dBc/Hz at 2 MHz offset frequency for a closed loop bandwidth of 1 MHz, when I_CP,max is equal to 2.6 mA. PLL locking time has been reduced with phase-noise cancellation and a constant loop bandwidth calibration circuits using the proposed CP unit current cell for the mismatch compensated PFD/DAC in wideband ΔΣ fractional-N PLL frequency synthesizer. Optimum phase noise performance can be achieved with the help of proposed design technique. Proposed ΔΣ fractional-N PLL frequency synthesizer is locked within 14.0 μs with an automatic frequency control circuit of the LC VCO and a constant loop bandwidth calibration circuit through the use of proposed CP unit current cell for the mismatch compensated PFD/DAC for the phase-noise cancellation in worst case condition of K_VFC = 10 and K_LBC = 150. Our new design technique can be extensively integrated for wideband fractional-N PLL for new type of wireless communication paradigm using the thinnest channel subharmonic transistor and low power devices, and it has the potential to open a new era of fractional-N PLLs for wideband application.