时分复用数字闭环电容式微加速度计接口电路

为实现电容式微加速度计的数字输出闭环,设计了一种数字输出闭环ASIC(Application Specific Integrated Circuit)接口电路,以降低电路输出噪声并提高测量量程。对已有的电容式微加速度计ASIC电路进行了改进,分时段在中间极板上加载差分电容读出信号和由脉宽调变(PWM)波控制的反馈信号,然后由控制器实现闭环,利用Sigma Delta调制器实现模数转换。通过分析差分电容读出电路和Sigma Delta调制器的原理和特性,建立了该数字输出闭环电容式微加速度计的模型,进行了系统的设计与仿真。实验结果表明,该数字输出闭环电容式微加速度计的噪声水平为9.6μg/√Hz,量程为±3g。这些结果验证了时分复用方案的可行性和本文所提出模型的正确性。

Interface circuit for digital close-loop capacitive microaccelerometer with time division multiplexing

To implement the digital close-loop for a capacitive microaccelerometer, a digital close-loop ASIC(Application Specific Integrated Circuit)was designed to reduce the output niose and to improve the measuring range of the interface circuit. The current interface circuit ASIC for the capacitive microaccelerometer was improved. A differential capacitance readout signal and a feedback signal controlled by Pulse Width Modulation(PWM) wave were applied to a middle plate sequentially, then the controller was used to operate the accelerometer to realize the close-loop configuration and a Sigma Delta modulator was used to perform the analog to digital conversion. The principle and characteristics for the capacitive microaccelerometer and the Sigma Delta modulator were analyzed, and a system model of the proposed digital close-loop capacitive microaccelerometer was built to implement the system design and simulation. The experiment on the capacitive microaccelerometer presents 9.6 μg/ Hz noise and an input range of about ±3g. The results indicate the interface circuit with Time Division Multiplexing works well in microaccelerometers and the proposed system model is correct.