一种高速DSP中延迟优化的乘累加单元的设计与实现

乘累加单元是任何数字信号处理器(DSP)数据通路中的一个关键部分.多年来,硬件工程师们一直倾注于其优化与改进.本文描述了一种速度优化的乘累加单元的设计与实现.本文的乘累加单元是为一种高速VLIW结构的DSP核设计,能够进行16×16 40的无符号和带符号的二进制补码操作.在关键路径延迟上,本文的乘累加单元比其他任何使用相同或不同算数技术实现的乘累加单元都更优.本文的乘累加单元已成功使用于synopsys的工具,并与synopsys的Design Ware库中相同位宽的乘累加单元比较.比较结果表明,本文的乘累加单元比Design Ware库中的任何其他实现都要快,适合于在需要高吞吐率的DSP核中使用.注意:比较是在Design compiler中使用相同属性和开关下进行的.

Design and Implementation of a Delay Optimized Multiply-Accumulate Unit for High Speed DSPs

The Multiply-Accumulate MAC] unit is a critical element in the data path of any DSP processor and has been a great focus of optimization by the hardware engineers in the last few years. This paper describes the design and implementation of a speed optimized MAC unit that is capable of performing 16×16+40 operations on unsigned and signed two's complement operands and is intended to be used in a high speed VLIW DSP Core. The proposed MAC is superior to the other MAC units implemented with the same or different algorithmic technologies in terms of critical delay. The said MAC has successfully been implemented, synthesized using synopsis tools and compared with the stream line MAC units of same data width from the synopsis design ware library. The comparison results showed that the proposed architecture is faster than all the other implementations from the synopsis's design ware IP library and is suitable for use in any DSP Core especially those requiring high throughput. Note: The comparison was taken under the same attributes and compile options.