按比例缩小器件栅隧穿电流分析模型

为了揭示半导体器件的栅隧穿电流与氧化层厚度之间的关系和MOS器件的静态特性，提出了一个栅隧穿电流与氧化层厚度关系的理论计算模型.采用SiO₂作为绝缘层介质并将晶体管尺寸按比例缩小，对于具有超薄氧化层的MOS器件，使用双重积分的方法构造计算模型，利用HSPICE对MOS器件的特性进行了详细研究，定量分析了MOS器件的工作情况，预测了在栅隧穿电流的影响下按比例缩小晶体管的特性变化趋势.利用BSIM4模型进行仿真的结果与所提出的理论模型相符合，为将来的电路设计提供了理论和实验依据.

Gate tunneling current analysis model for scaled devices

In order to reveal the relationship between gate tunneling current and oxide thickness of scaled semiconductor as well as the static characteristics of MOS devices, a theoretical calculation model for the relationship between gate tunneling current and oxide thickness was presented. Using SiO₂ as the dielectric and scaling down the transistor, the characteristics of MOS devices with ultra thin oxide layer were studied by means of HSPICE simulator and double integral calculation model. The working status of MOS devices was quantitatively analyzed, and the varying trends in the scaled transistor characteristics under the effect of gate tunneling current were predicted. The simulation results with BSIM4 model well agree with the 〖JP3〗proposed theoretical model, which can provide the theoretical and experimental basis for future circuit design.