| 基于FPGA的CSD编码乘法器 |
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| 引用本文： | 何永泰,黄文卿.基于FPGA的CSD编码乘法器[J].电子测量技术,2006,29(4):87-88. |
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| 作者姓名： | 何永泰 黄文卿 |
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| 作者单位： | 楚雄师范学院物理与电子科学系,楚雄,675000 |
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| 摘 要： | 在数字滤波、离散傅里叶变换等数字信号处理中,乘法运算是一个最基本的运算,乘法运算的速度决定着数字系统的运算速度。本文通过理论与实验研究相结合的方法介绍CSD编码乘法器的运算法则及其在FPGA中的实现过程。通过与二进制乘法器相比较,证明CSD编码乘法器在减少对FPGA资源的占用和提高运算速度方面具有明显的效果。
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| 关 键 词： | CSD编码 乘法器 FPGA |
Research on multiplier of CSD based on FPGA |
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| He Yongtai,Huang Wenqing.Research on multiplier of CSD based on FPGA[J].Electronic Measurement Technology,2006,29(4):87-88. |
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| Authors: | He Yongtai Huang Wenqing |
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| Affiliation: | Department of Physics and Electron Science, Chuxiong Normal University, Chuxiong 675000 |
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| Abstract: | In DSP of digital filters and Fourier transforms, multiplication is a basis operation. The speed of operation of digital system was determined by the speed of the multiplication. Theorem of multiplier of CSD and process of realization in FPGA were introduced by method of theory and experimentation. The effect was proved in reducing consumption of FPGA resource and improving speed of operation. |
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| Keywords: | CSD(canonic signed digit) multiplier FPGA (field programmable gate array) |
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