A microprocessor with a 128-bit CPU, ten floating-point MAC's, fourfloating-point dividers, and an MPEG-2 decoder |
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| Authors: | Suzuoki M Kutaragi K Hiroi T Magoshi H Okamoto S Oka M Ohba A Yamamoto Y Furuhashi M Tanaka M Yutaka T Okada T Nagamatsu M Urakawa Y Funyu M Kunimatsu A Goto H Hashimoto K Ide N Murakami H Ohtaguro Y Aono A |
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| Affiliation: | Sony Comput. Entertainment Inc., Tokyo; |
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| Abstract: | A 250-MHz microprocessor intended for home computer entertainment consists of a CPU core with 128-b multimedia extensions, two single-instruction, multiple-data (SIMD) very long instruction word (VLIW) vector processors containing ten floating-point multiplier accelerators and four floating-point dividers, an MPEG-2 decoder, a ten-channel direct memory access (DMA) controller, and other peripherals with 128 b internal buses on one die. The core is a two-way superscalar MIPS-compatible microprocessor with 16-kB scratch-pad RAM. Each vector processor is a five-way SIMD-VLIW architecture, which is tightly dedicated for specific applications concerning three-dimensional geometry calculation and physical simulation. A DMA controller connects between main memory and each processor's local memory to conceal memory access penalty. It contains 10.5 M transistors in 17×14.1 mm and dissipates 15 W at 1.8 V |
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