Voltage stability boundary and margin enhancement with FACTS and HVDC

Voltage stability is a major concern of today’s power system, especially under heavily loaded conditions because of reactive power limits. FACTs devices are very effective solution to prevent voltage instability and voltage collapse due to fast and very flexible control. In this paper, the impacts of SVC, STATCOM, TCSC and HVDC on voltage stability boundary (VSB) in P–Q plane have been studied. The bus impedance matrix and load flow results are used to find the voltage stability boundary. The Z_bus is modified to take into account the effect of FACTS on VSB. The variable susceptance model for SVC and variable series impedance power flow model for TCSC are used in Newton Raphson’s method. The STATCOM is modelled as variable voltage source connected in series with an equivalent impedance of the shunt connected transformer. Similarly HVDC is also modelled as two STATCOMs connected at each end of the line one as rectifier and another as inverter. Some important bus and line stability indices are evaluated to determine the most effective location for SVC/STATCOM and TCSC/HVDC respectively in order to achieve the maximum enhancement of voltage stability margin. The study has been carried out on IEEE-14 bus and IEEE-30 bus test systems using MATLAB programming. A comprehensive study is done to compare the effectiveness of FACTS devices and HVDC on voltage stability margins.